A self-timed trigger circuit with single-rail data input refers to pulse and computational technique and may be used for designing self-timed trigger circuit, register and computational units, as well as in digital signal processing system as both storage cell and interface between synchronous and self-timed parts of one design.
There is known trigger [1] consisting of four AND-NOT elements and inverter.
Disadvantage of this trigger is an absence of means of transition termination indication.
The nearest to the suggested solution by technical nature and accepted as a prior art is the self-timed trigger circuit [2] containing storage unit which consists of bistable cell on base of AND-OR-NOT elements with paraphase data input and output, and indication element AND-OR-NOT.
Disadvantage of prior art is that it works only with paraphase or dual-rail data, which double a number of data connections between multibit input data source and register on base of such trigger, and does not allow to use it as an element of interface between synchronous and self-timed circuits.